Source:http://linkedlifedata.com/resource/pubmed/id/17831442
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| Predicate | Object |
|---|---|
| rdf:type | |
| lifeskim:mentions | |
| pubmed:issue |
5025
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| pubmed:dateCreated |
2010-6-8
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| pubmed:abstractText |
The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. This is the cumulative result of architectural improvements as well as increases in circuit speed. Moreover, this improvement has been obtained in a transparent fashion, that is, without requiring programmers to rethink their algorithms and programs, thereby enabling the tremendous proliferation of computers that we see today. To continue this performance growth, microprocessor designers have incorporated instruction-level parallelism (ILP) into new designs. ILP utilizes the parallel execution ofthe lowest level computer operations-adds, multiplies, loads, and so on-to increase performance transparently. The use of ILP promises to make possible, within the next few years, microprocessors whose performance is many times that of a CRAY-IS. This article provides an overview of ILP, with an emphasis on ILP architectures-superscalar, VLIW, and dataflow processors-and the compiler techniques necessary to make ILP work well.
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| pubmed:language |
eng
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| pubmed:journal | |
| pubmed:status |
PubMed-not-MEDLINE
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| pubmed:month |
Sep
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| pubmed:issn |
0036-8075
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| pubmed:author | |
| pubmed:issnType |
Print
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| pubmed:day |
13
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| pubmed:volume |
253
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| pubmed:owner |
NLM
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| pubmed:authorsComplete |
Y
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| pubmed:pagination |
1233-41
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| pubmed:year |
1991
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| pubmed:articleTitle |
Instruction-level parallel processing.
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| pubmed:publicationType |
Journal Article
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