Linked Life Data

17025511

Source:http://linkedlifedata.com/resource/pubmed/id/17025511

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PredicateObject
rdf:type
lifeskim:mentions
pubmed:issue
2 Pt 2
pubmed:dateCreated
2006-10-9
pubmed:abstractText
Recent progress in integrated circuit technologies requires precise evaluation between dynamic characteristics and topological architecture design. In this paper, we have investigated the performance evaluation of network-on-chip (NoC) architectures constructed with diverse scale-free network topologies by dynamic packet traffic simulation and theoretical network analysis. Topological differences of scale-free networks are evaluated by the degree-degree correlations that indicate topological tendency between the degree of a node and that of the nearest neighbors. Our simulation results quantitatively show that the NoC architecture constructed with the topology where hubs mostly connect to lower-degree nodes is found to achieve short latency and low packet loss ratio since it can disperse traffic load and avoid the extreme concentration of load on hubs.
pubmed:language
eng
pubmed:journal
pubmed:status
PubMed-not-MEDLINE
pubmed:month
Aug
pubmed:issn
1539-3755
pubmed:author
pubmed:issnType
Print
pubmed:volume
74
pubmed:owner
NLM
pubmed:authorsComplete
Y
pubmed:pagination
026115
pubmed:year
2006
pubmed:articleTitle
Packet traffic analysis of scale-free networks for large-scale network-on-chip design.
pubmed:affiliation
Department of Advanced Interdisciplinary Studies, and Research Center for Advanced Science and Technology, The University of Tokyo, Tokyo 153-8904, Japan.
pubmed:publicationType
Journal Article